1. Field of the Invention
Embodiments of the invention relate generally to semiconductor memory devices. More particularly, embodiments of the invention relate to volatile semiconductor memory devices having a local sense amplifier.
A claim of priority is made to Korean Patent Application No. 10-2006-0046868, filed on May 25, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
There is a continuing demand for volatile semiconductor memory devices such as dynamic random access memory (DRAM) to become increasingly integrated and to operate at higher clock speeds. Conventional DRAM devices are often used, for example, as main memories in electronic devices and therefore increasing their level of integration and speed tends to improve the performance of the electronic devices.
As the level of integration in volatile memory devices such as DRAMs continues to increase, the level of an operating voltage used to perform data access operations such as read and write operations in the devices tends to decrease accordingly. As the operating voltage of the devices decreases, a current difference between lines in data input/output (IO) line pairs of memory cells in the devices tends to decrease accordingly. As a result of this decrease in the current difference between the lines of the data IO line pairs, a sensing margin of the memory cells decreases as well.
To help explain some problems associated with the decreased sensing margin, examples of read and write operations for a conventional DRAM device are explained below.
A conventional DRAM device includes memory cells comprising an access transistor and a storage capacitor. To maintain stored data in the memory cells, a periodic refresh operation is generally required.
A read operation for a memory cell in the conventional DRAM device is typically performed using a method wherein a column selection gate opens and current flows through an IO line of a current sense amplifier associated with the memory cell and a bit line in a bit line pair maintained at a relatively low potential.
A resulting difference in the amount of current flowing through both lines in the bit line pair is then sensed to determine the logic state of the memory cell. Unfortunately, as the memory cell density of DRAMs increases and cell data is input and output at higher frequencies, the required sensing margin of a sense amplifier used to sense the current difference tends to decrease accordingly. As a result, it becomes increasingly difficult to accurately sense the logic state of the memory cell.
FIG. 1 is a circuit diagram of a conventional sense amplifier circuit for use in a semiconductor memory device. Referring to FIG. 1, the sense amplifier circuit comprises a bit line sense amplifier (BLSA) 200 connected between a bit line pair comprising a bit line BL and a complimentary bit line BLB. The sense amplifier circuit further comprises a current sense amplifier 300 connected between a global data IO line pair comprising a global data IO line GIO and a complimentary global data IO line GIOB. Current sense amplifier 300 functions as an IO sense amplifier.
Memory cells are connected between corresponding bit lines among bit line pairs such as that illustrated in FIG. 1, and word lines (not shown), forming a matrix-type memory cell array. Bit line sense amplifier 200 includes a P-type portion comprising P-type metal-oxide semiconductor (MOS) transistors P7 and P8, and an N-type portion comprising N-type MOS transistors N9 and N10. Bit line sense amplifier 200 is connected to one or more bit line pairs associated with one or more memory cells.
In a read operation involving the sense amplifier circuit shown in FIG. 1, a column selection line CSL and a multiplexing signal MUXON are both activated (i.e., set to a voltage level “high”). As a result, a column selection gate comprising negative metal-oxide semiconductor (NMOS) transistors N3 and N4 is turned on, along with switching transistors N1 and N2. NMOS transistor N1 connects complementary local data IO line LIOB with complementary global data IO line GIOB, NMOS transistor N2 connects local data IO line LIO with global data IO line GIO, NMOS transistor N3 connects bit line BL with local data IO line LIO, and NMOS transistor N4 connects complementary bit line BLB with complementary local data IO line LIOB. Load transistors P1 and P2 are turned on by a load control signal PLOADON to supply current during the read operation.
During the read operation, P-type transistors P3 and P4 are turned on by a switching signal PWRD. Where bit lines BL and BLB have a voltage level difference during the read operation, current will flow through PMOS transistor P1 and bit line BL with a different magnitude than through PMOS transistor P2 and complementary bit line BLB. For example, where a memory cell connected to bit line BL stores data with a relatively low voltage level compared with complimentary bit line BLB, a relatively larger current will flow in a current path along PMOS transistor P1, global data IO line GIO, local data IO line LIO and bit line BL, than in a current path along PMOS transistor P2, complementary global data IO line GIOB, complementary local data IO line LIOB and complementary bit line BLB.
In this case, a different amount of current will flow through a sense input node NO2 and a sense input node NO1 of current sense amplifier 300. Current sense amplifier 300 is a cross coupled-type current amplifier comprising of PMOS transistors P5 and P6 and diode-coupled NMOS transistors N5 and N6. Current sense amplifier 300 senses and amplifies the difference in the amount of current flowing through sense input nodes NO1 and NO2 by operation of transistors P5, P6, N5 and N6. As a result, current sense data CSA and CSAB is produced at respective sense output nodes NO3 and NO4. Current sense data CSA and CSAB is input to a voltage sense amplifier (not shown), and the voltage sense amplifier produces one or more output signals indicative of the logic state of the memory cell.
As the density of DRAM devices increases and memory cell transistors become smaller, the difference in magnitude between current on bit line BL and complementary bit line BLB during read operations tends to decrease accordingly. Where the current difference becomes too small, current sense amplifier 300 may not be able to appropriately amplify the current difference and read operations may fail. In other words, current sense data CSA and CSAB may not be informative as to the logic state of a corresponding memory cell. To further illustrate this, a sensing failure is described below in relation to FIGS. 3 and 4.
Referring to FIG. 3, in a read operation of the sense amplifier circuit, column selection line CSL and multiplexing signal MUXON are activated. As a result, a current difference is generated between sense input nodes NO1 and NO2 of current sense amplifier 300. The current difference is illustrated in FIG. 3 by the waveform labeled Δi(CSA). Current sense amplifier 300 senses and amplifies the current difference between sense input nodes NO1 and NO2 to produce output signals having waveforms such as those labeled CSA/CSAB in FIG. 3 through two output nodes NO3 and NO4, respectively.
Unfortunately, as the density of memory cells increases and the resistance of IO lines increases (e.g., by decreasing line width), the current difference between sense input nodes NO1 and NO2 of current sense amplifier 300 tends to decrease accordingly, as illustrated by the waveform labeled Δi(CSA) in FIG. 4. As a result, the output signals apparent at output nodes NO3 and NO4 become attenuated, as illustrated by the waveform labeled CSA/CSAB in FIG. 4. The attenuation of the output signals apparent at output nodes NO3 and NO4 may cause a failure in the read operation. In addition, as the current difference between sense input nodes NO1 and NO2 decreases, minor mismatches between the MOS transistors forming current sense amplifier 300 due to manufacturing process variation may also give rise to failures in the read operation.
To prevent failures from occurring in read operations, some conventional sense amplifiers such as that illustrated in FIG. 2 include a local sense amplifier. FIG. 2 illustrates a conventional sense amplifier circuit having a local sense amplifier and FIGS. 5 and 6 illustrate the timing of a read operation performed with the sense amplifier circuit of FIG. 2.
Referring to FIG. 2, a differential amplifier type local sense amplifier 100 is installed between BLSA 200 and current sense amplifier 300 shown in FIG. 1. In addition, a precharge transistor P9 is connected to complementary local data IO line LIOB to precharge complementary local data IO line pair LIOB and a precharge transistor P10 is connected to local data IO line LIO to precharge local data IO line LIO.
Local sense amplifier 100 shown in FIG. 2 amplifies the current difference between the inputs of current sense amplifier 300. However, the benefits of local sense amplifier 100 may be lost when the sense amplifier circuit is operated at a high frequency.
A read operation of the sense amplifier circuit of FIG. 2 is described below with reference to FIGS. 5 and 6.
Referring to FIG. 5, in the read operation, column selection line CSL is activated while multiplexing signal MUXON is deactivated (i.e., set to a voltage level “low”). At the same time, a precharge signal LIOPRE is activated to precharge complementary local data IO line LIOB and local data IO line LIO, and a sense amplifier control signal PLSAEN is activated to enable local sense amplifier 100. When precharge signal LIOPRE is activated, a precharge operation of precharge transistors P9 and P10 stops. While switching transistors N1 and N2 are turned off, local sense amplifier 100 amplifies the difference between the respective voltage levels of complementary local data IO line LIOB and local data IO line LIO by operation of transistors N11 through N15.
In FIG. 5, the difference between the voltage levels of complementary local data IO line LIOB and local data IO line LIO is represented by the waveform labeled LIO/LIOB. This difference causes a corresponding change in the respective voltage levels of complementary global data IO line GIOB and global data IO line GIO, which in turn causes an increase in the current difference between sense input nodes NO1 and NO2 of current sense amplifier 300, as illustrated by the waveform labeled Δi(CSA) in FIG. 5. Current sense amplifier 300 senses and amplifies the current difference between sense input nodes NO1 and NO2 to produce output signals having waveforms such as those labeled CSA/CSAB in FIG. 5 through output nodes NO3 and NO4, respectively.
Unfortunately, in a high frequency operation, there may not be enough time to completely precharge complementary local data IO line LIOB and local data IO line LIO, and as a result, current sense amplifier 300 may have difficulty producing current sense data CSA and CSAB within a desired time frame. For example, as illustrated by the reference numeral D1 in FIG. 6, the output signals of the sense amplifier circuit fail to develop at the correct time during high-frequency operation.
In sum, in the sense amplifier circuit of FIG. 2, the voltage level of complementary local data IO line LIOB and local data IO line LIO is increased in order to increase the respective input currents of current sense amplifier 300. However, the performance of the sense amplifier circuit tends to suffer at high frequencies due at least in part to the difficulty of precharging complementary local data IO line LIOB and local data IO line LIO. Therefore, the sense amplifier circuit of FIG. 2 has limited applicability in highly integrated memories operating at high speeds.